Semiconductor integrated circuit devices are well known in the art. In particular, in the field of memory devices, including both volatile (such as DRAM or SRAM) as well as nonvolatile (such as FLASH), a plurality of polysilicon lines are used as row lines to access various memory cells. Because these row lines are made out of polysilicon, they tend to have higher resistivity than conductors made out of metal. Thus, metal lines are used to “strap” various polysilicon lines. By strapping it is meant to connect a metal line in parallel with the polysilicon row line to reduce the resistivity of the polysilicon row line.
As the scale of integration increases, i.e., the smallest dimension of a feature in a semiconductor integrated circuit device decreases, the width of the polysilicon lines will also decrease. However, the scale of integration for metal lines has not kept pace at the same rate as the scale of integration for other features such as the polysilicon lines. In other words, the width of the metal strapping lines has not been reduced at the same rate as the width of the polysilicon lines.
Thus, a metal line having a width greater than a plurality of polysilicon lines, may be segmented into a plurality of metal segments with each metal segment used to strap a different portion of the polysilicon lines.
The present invention deals with the optimal position for the strapping of such a partial strapped polysilicon line. U.S. Pat. No. 6,455,942 discloses one such technique, and its disclosure is incorporated herein by reference in its entirety. However, U.S. Pat. No. 6,455,942 deals with the problem of partial strapping by modeling the polysilicon lines as purely resistive loads without any capacitance.
Using the delay of Elmore technique to solve the problem of delay in RC networks has been know in the prior art. See, for example, “Signal Delay in General RC Networks” by Tzu-Mu Lin and Carver Mead, IEEE Transactions on Computer Aided Design, vol. CAD-3, No. 4, October 1984 (pp. 331-349); “Splitting of RC Network for Accurate Model Reduction” by Patricia Renault and Pirouz Bazargan-Sabet, IEEE, 2004 (pp. 734-737); and “Computing Signal Delay in General RC Networks by Tree/Link Partitioning” by Pak K. Chan and Kevin Karplus, 26th ACM/IEEE Design Automation Conference, 1989 (pp. 485-490).